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general description the max1716/MAX1854/max1855 step-down con- trollers are intended for core cpu dc-dc converters in notebook computers. they feature a dynamically adjustable output (5-bit dac), ultra-fast transient response, high dc accuracy, and high efficiency need- ed for leading-edge cpu core power supplies. maxim's proprietary quick-pwm quick-response, constant-on- time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant-on response to load transients while maintaining a relative- ly constant switching frequency. the max1716/MAX1854/max1855 are designed specifically for cpu core applications requiring a volt- age-positioned supply. the voltage-positioning input (vps), combined with a high dc accuracy control loop, is used to implement a power supply that modifies its output set point in response to the load current. this arrangement decreases full-load power dissipation and reduces the required number of output capacitors. the 28v input range of the max1716/MAX1854/max1855 enables single-stage buck conversion from high-volt- age batteries for the maximum possible efficiency. alternatively, the devices?high-frequency capability combined with two-stage conversion (stepping down the +5v system supply instead of the battery) allows the smallest possible physical size. the output voltage can be dynamically adjusted through the 5-bit digital- to-analog converter (dac) inputs. the max1716/MAX1854/max1855 are available in a 24-pin qsop package. for applications requiring speedstep power control (see the max1717). ________________________applications notebook computers docking stations cpu core supply single-stage (batt to v core ) converters two-stage (+5v to v core ) converters features high-efficiency voltage positioning quick-pwm architecture ?% v out line-regulation accuracy adjustable output range (5-bit dac) max1716: 0.925v to 1.6v MAX1854: 0.925v to 2.0v max1855: 0.600v to 1.75v 2v to 28v input range 200/300/400/550khz switching frequency output undervoltage protection overvoltage protection (max1716/max1855) drive large synchronous-rectifier mosfets 1.7ms digital soft-start 700 a i cc supply current 1 a shutdown supply current 2v ?% reference output v gate transition-complete indicator small 24-pin qsop package max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ________________________________________________________________ maxim integrated products 1 19-1758; rev 0; 8/00 for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. pin configuration appears at end of data sheet. quick-pwm is a trademark of maxim integrated products. speedstep is a trademark of intel corp. ordering information part temp. range pin-package max1716 eeg -40 c to +85 c 24 qsop MAX1854 eeg -40 c to +85 c 24 qsop max1855 eeg -40 c to +85 c 24 qsop typical operating circuit vgate dh lx dl cs vps bst +5v input ref ilim d0 d1 d2 d3 d4 skip cc gnd pgnd fb max1716 MAX1854 max1855 ton v+ v cc v dd shdn output dac inputs battery 2v to 28v
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, skip = v cc , vps = pgnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: skip may be forced below -0.3v, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto- type breadboards, using the no-fault test mode. limit the current drawn to -2ma (max). v+ to gnd ..............................................................-0.3v to +30v v cc , v dd to gnd .....................................................-0.3v to +6v pgnd to gnd.....................................................................0.3v shdn , vgate to gnd .............................................-0.3v to +6v ilim, fb, cc, ref, d0 d4, vps, ton to gnd ...........................................-0.3v to (v cc + 0.3v) skip to gnd (note 1).................................-0.3v to (v cc + 0.3v) dl to pgnd................................................-0.3v to (v dd + 0.3v) bst to gnd ............................................................-0.3v to +36v dh to lx ....................................................-0.3v to (v bst + 0.3v) lx to bst..................................................................-6v to +0.3v cs to gnd.................................................................-2v to +30v ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70 c) 24-pin qsop (derate 9.5mw/ c above +70 c)...........762mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units pwm controller battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v dac codes from 1.35v to 2.0v -1 1 dac codes from 0.925v to 1.3v -1.2 1.2 dc output voltage accuracy (notes 2, 3) v+ = 4.5v to 28v, vps = pgnd dac codes from 0.6v to 0.9v -1.5 1.5 % fb input bias current i fb fb = 0.6v to 2.0v -0.2 0.2 a vps input bias current i vps v vps = 40mv -1 1 a vps gain a vps v vps = 0 or -40mv, gain from vps to fb 0.153 0.175 0.197 %/mv cs input bias current i cs 0 to 28v -1 1 a ilim input leakage current i ilim v ilim = 0 or 5.0v 0.01 100 na soft-start ramp time 0 to full ilim 1.7 ms ton = gnd 205 255 300 ton = ref 280 327 375 ton = open 425 470 520 on-time (note 4) t on v+ = 11.0v, v fb = 1.5v ton = v cc 615 678 740 ns minimum off-time (note 4) t off ( m in ) 400 500 ns
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, skip = v cc , vps = pgnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point 700 950 a quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point <1 5 a quiescent supply current (v+) i+ 25 40 a shutdown supply current (v cc ) shdn = gnd <1 5 a shutdown supply current (v dd ) shdn = gnd <1 5 a shutdown supply current (v+) shdn = gnd, v cc = v dd = 0 or 5v <1 5 a reference voltage v ref v cc = 4.5v to 5.5v, no external ref load 1.98 2 2.02 v reference load regulation i ref = 0 to 50 a 0.01 v ref sink current i ref ref in regulation 10 a ref fault lockout voltage falling edge 1.6 v fault protection max1716 1.8 1.9 2.0 output overvoltage fault threshold (note 5) measured at fb max1855 1.97 2.0 2.03 v output overvoltage fault propagation delay (note 5) fb forced to 2% above trip threshold (max1716/max1855 only) 1.5 s output undervoltage fault threshold (foldback) 35 40 45 % output undervoltage fault propagation delay fb forced to 2% below trip threshold 10 s output undervoltage fault blanking time (foldback) from shdn signal going high 10 30 ms current-limit threshold (positive, default) v ith v pgnd - v cs , ilim = v cc 110 120 130 mv v ilim = 0.5v 40 50 60 current-limit threshold (positive, adjustable) v ith v pgnd - v cs v ilim = 2v (ref) 170 200 230 mv negative current-limit threshold v pgnd - v cs -1.2 v ith mv zero-crossing current-limit threshold v pgnd - v cs 3mv thermal shutdown threshold hysteresis = 10 c 150 c v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, switching disabled below this level 4.0 4.45 v
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, skip = v cc , vps = pgnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units vgate lower trip threshold measured at fb with respect to unloaded output voltage, falling edge -12.5 -10 -7.5 % vgate upper trip threshold measured at fb with respect to unloaded output voltage, rising edge 7.5 10 12.5 % vgate propagation delay falling edge, fb forced 2% below or above vgate trip threshold 1.5 s vgate output low voltage i sink = 1ma 0.4 v vgate leakage current high state, forced to 5.5v 1 a gate drivers dh gate driver on-resistance r on ( d h ) v bst - v lx forced to 5v 1.3 5 ? high state (pullup) 1.5 5 dl gate driver on-resistance r on ( dl ) low state (pulldown) 0.5 1.7 ? dh gate driver source/sink current i dh dh forced to 2.5v, v bst - v lx forced to 5v 1 a dl gate drive sink current i dl dl forced to 5v 3 a dl gate driver source current i dl dl forced to 2.5v 1 a dl rising 35 dead-time dh rising 26 ns logic and i/o logic input high voltage v ih d0 ? d4, shdn , skip 2.4 v logic input low voltage v il d0 ? d4, shdn , skip 0.8 v ton = v cc (200khz operation) v cc - 0.4 ton = open (300khz operation) 3.15 3.85 ton = ref (400khz operation) 1.65 2.35 ton input levels ton = gnd (550khz operation) 0.5 v ton = gnd or v cc -3 3 logic input current shdn , skip = gnd or v cc -1 1 a d0 ? d4 pullup current d0 ? d4 = gnd 3 5 10 a skip no-fault mode current t a = +25 c -1.5 -0.1 ma
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, skip = v cc , vps = pgnd, t a = -40 c to +85 c , unless otherwise noted.) (note 6) parameter symbol conditions min typ max units pwm controller battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v dac codes from 1.35v to 2.0v -1.6 1.6 dc output voltage accuracy (notes 2, 3) v+ = 4.5v to 28v, vps = pgnd dac codes from 0.6v to 1.3v -2 2 % fb input bias current i fb fb = 0.6v to 2.0v -0.2 0.2 a vps input bias current i vps v vps = 40mv -1 1 a vps gain a vps v vps = 0 or -40mv, gain from vps to fb 0.153 0.197 %/mv cs input bias current i cs 0 to 28v -1 1 a ilim input leakage current i ilim v ilim = 0 or 5.0v 100 na ton = gnd 205 300 ton = ref 280 375 ton = open 425 520 on-time (note 4) t on v+ = 11.0v, v fb = 1.5v ton = v cc 615 740 ns minimum off-time (note 4) t off ( m in ) 500 ns bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point 950 a quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point 5 a quiescent supply current (v+) i+ 40 a shutdown supply current (v cc ) shdn = gnd 5 a shutdown supply current (v dd ) shdn = gnd 5 a shutdown supply current (v+) s hdn = gn d , v + = 28v , v c c = v d d = 0 or 5v 5 a reference voltage v ref v cc = 4.5v to 5.5v, no external ref load 1.98 2.02 v reference load regulation i ref = 0 to 50 a 0.01 v ref sink current i ref ref in regulation 10 a fault protection max1716 1.8 2.0 v output overvoltage fault threshold (note 5) measured at fb max1855 1.97 2.03 output undervoltage fault threshold (foldback) 35 45 % output undervoltage fault blanking time (foldback) from shdn signal going high 10 30 ms
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 6 _______________________________________________________________________________________ note 2: output voltage accuracy specifications apply to dac voltages from 0.6v to 2.0v. includes load-regulation error. note 3: when the inductor is in continuous conduction, the output voltage will have a dc regulation level higher than the error-com- parator threshold by 50% of the ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage will have a dc regulation level higher than the trip level by approximately 1.5% due to slope compensation. note 4: on-time and off-time specifications are measured from 50% to 50% at the dh pin, with lx forced to 0, bst forced to 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times may be different due to mosfet switching speeds. note 5: the MAX1854 does not have overvoltage protection. note 6: specifications to -40 c are guaranteed by design, not production tested. electrical characteristics (continued) (circuit of figure 1, v+ = +15v, v cc = v dd = 5v, skip = v cc , vps = pgnd, t a = -40 c to +85 c , unless otherwise noted.) (note 6) parameter symbol conditions min typ max units current-limit threshold (positive, default) v ith v pgnd - v cs , ilim = v cc 100 140 mv v ilim = 0.5v 35 65 current-limit threshold (positive, adjustable) v ith v pgnd - v cs v ilim = 2v (ref) 160 240 mv v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, switching disabled below this level 4.0 4.45 v vgate lower trip threshold measured at fb with respect to unloaded output voltage, falling edge -12.5 -7.5 % vgate upper trip threshold measured at fb with respect to unloaded output voltage, rising edge 7.5 12.5 % vgate output low voltage i sink = 1ma 0.4 v vgate leakage current high state, forced to 5.5v 1 a gate drivers dh gate driver on-resistance r on ( d h ) v bst - v lx forced to 5v 5 ? high state (pullup) 5 dl gate driver on-resistance r on ( dl ) low state (pulldown) 1.7 ? logic and i/o logic input high voltage v ih d0 ? d4, shdn , skip 2.4 v logic input low voltage v il d0 ? d4, shdn , skip 0.8 v ton = v cc (200khz operation) v cc - 0.4 ton = open (300khz operation) 3.15 3.85 ton = ref (400khz operation) 1.65 2.35 ton input levels ton = gnd (550khz operation) 0.5 v ton = gnd or v cc -3 3 logic input current shdn , skip = gnd or v cc -1 1 a d0 ? d4 pullup current d0 ? d4 = gnd 3 10 a
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning _______________________________________________________________________________________ 7 max1716-01 100 50 0.01 10.1 1 10 100 efficiency vs. load current (2.0v at 300khz) 60 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 a1 c1 d1 a2 b2 c2 d2 MAX1854 only b1 max1716-02 100 b1 d1 d2 50 0.01 10.1 1 10 100 efficiency vs. load current (1.6v at 300khz) 60 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 a1 c1 a2 b2 c2 skip mode (skip = gnd) a1: v batt = 4.5v b1: v batt = 7v c1: v batt = 15v d1: v batt = 24v pwm mode (skip = v cc ) a2: v batt = 4.5v b2: v batt = 7v c2: v batt = 15v d2: v batt = 24v 100 50 0.01 0.1 1 10 100 efficiency vs. load current (1.3v at 200khz) 60 max1716-03 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 circuit #2 l = 1.5 h d2 c2 a2 b2 c1 b1 a1 d1 100 50 0.01 0.1 1 10 100 efficiency vs. load current (1.3v at 300khz) 60 max1716-04 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 circuit #2 l = 1.0 h c2 d2 a2 b2 d1 c1 b1 a1 100 50 0.01 0.1 1 10 100 efficiency vs. load current (1.3v at 550khz) 60 max1716-05 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 d2 c2 d1 b2 a2 c1 b1 a1 circuit #2 l = 0.68 h 100 50 0.01 0.1 1 10 100 effective efficiency vs. load current (1.3v at 200khz) 60 max1716-06 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 circuit #2 l = 1.5 h d2 c2 b2 a2 a1 b1 c1 d1 100 50 0.01 0.1 1 10 100 effective efficiency vs. load current (1.3v at 300khz) 60 max1716-07 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 d2 c2 b2 a2 c1 b1 a1 d1 circuit #2 l = 1.0 h 100 50 0.01 0.1 1 10 100 effective efficiency vs. load current (1.3v at 550khz) 60 max1716-08 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 d2 c2 b2 a2 c1 b1 a1 d1 circuit #2 l = 0.68 h typical operating characteristics (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.)
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 8 _______________________________________________________________________________________ 100 50 0.01 0.1 1 10 100 efficiency vs. load current (1.0v at 400khz) 60 max1716-09 load current (a) efficiency (%) 70 80 90 85 75 65 55 95 circuit #3 d2 c2 a2 c1 b1 a1 d1 b2 max1716-10 1.50 1.54 1.52 1.58 1.56 1.62 1.60 1.64 010 515 load current (a) 20 25 v batt = 24v v batt = 7v output voltage vs. load current (1.6v at 300khz) output voltage (v) pwm mode skip mode 1.20 1.24 1.22 1.28 1.26 1.32 1.30 1.34 046 2 8 10 12 14 output voltage vs. load current (1.3v at 300khz) max1716-11 load current (a) output votlage (v) circuit #2 l = 1.0 h v batt = 24v v batt = 7v pwm mode skip mode 0.92 0.96 0.94 1.00 0.98 1.02 046 2 8 10 12 14 output voltage vs. load current (1.0v at 400khz) max1716-12 load current (a) output votlage (v) circuit #3 v batt = 24v v batt = 7v pwm mode skip mode 0 100 50 200 150 300 250 350 08 4 121620 switching frequency vs. load current max1716-13 load current (a) frequency (khz) pwm mode skip mode v batt = 7v v out(prog) = 1.6v 260 280 270 300 290 310 320 0812 4 162024 switching frequency vs. battery voltage max1716 -14 v batt (v) frequency (khz) v out(prog) = 1.6v v out(prog) = 0.925v i out = 12a 270 290 280 310 300 320 330 -40 10 -15 356085 switching frequency vs. temperature temperature ( c) switching frequency (khz) max1716-15 i out = 12a i out = 5a i out = 1a 0.74 0.78 0.76 0.82 0.80 0.86 0.84 0.88 on-time ( s) max1716-16 -40 10 -15 35 60 85 on-time vs. temperature temperature ( c) i out = 12a i out = 5a i out = 1a -6 -2 -4 2 0 4 6 current-limit error (%) max1716-17 -40 10 -15 356085 normalized current-limit error vs. temperature temperature ( c) typical operating characteristics (continued) (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.)
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning _______________________________________________________________________________________ 9 -3 -1 -2 1 0 2 3 0 1.0 1.5 0.5 2.0 2.5 3.0 current-limit error vs. v ilim v ilim (v) error (%) max1716-18 0 1.0 0.5 2.5 2.0 1.5 4.0 3.5 3.0 4.5 08 4 12162024 continuous-to-discontinuous inductor current point v batt (v) output current (a) max1716-19 circuit#1 v out = 1.6v circuit#2 v out = 1.3v circuit#3 v out = 1.0v 0 5 15 10 20 25 inductor current peaks and valleys vs. battery voltage inductor current (a) max1716-20 08 4 121620 v out = 1.3v circuit#2 (l = 1 h) 24 i peak i valley v batt (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 08 4 12162024 no-load supply current vs. battery voltage v batt (v) supply current (ma) max1716-21 skip mode 550khz (ton = gnd) curcuit#2 (l = 0.68 h) i cc + i dd i batt 0 10 5 20 15 25 30 max1716-22 08 4 12162024 no-load supply current vs. battery voltage v batt (v) supply current (ma) pwm mode 550khz (ton = gnd) curcuit#2 (l = 0.68 h) i cc + i dd i batt 0 4 2 8 6 12 10 14 max1716-23 08 4 12162024 no-load supply current vs. battery voltage v batt (v) supply current (ma) pwm mode 200khz (ton = v cc ) curcuit#2 (l = 1.5 h) i cc + i dd i batt b 10a 0 20a 1.55v 1.60v 1.50v a 40 s/div a. v out = 1.6v, 50mv/div; b. i out = 1.3a to 18a, 10a/div; circuit #1, v batt = 15v, pwm mode load-transient response (v batt = 15v, pwm mode) max1716-24 b 10a 0 20a 1.55v 1.60v 1.50v a 40 s/div a. v out = 1.6v, 50mv/div; b. i out = 0.3a to 18a, 10a/div; circuit #1, v batt = 15v, pwm mode; vps = pgnd load-transient response with disabled voltage positioning max1716-25 typical operating characteristics (continued) (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.)
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 10 ______________________________________________________________________________________ b 10a 0 20a 1.55v 1.60v 1.50v a 40 s/div a. v out = 1.6v, 50mv/div b. i out = 0.3a to 18a, 10a/div circuit #1, v batt = 4.5v, pwm mode load-transient response (v batt = 4.5v) max1716-27 b 10a 0 20a 0.94v 0.98v 1.00v 0.96v a 40 s/div a. v out = 1.0v, 20mv/div b. i out = 0.3a to 12a, 10a/div circuit #3, v batt = 4.5v, pwm mode load-transient response (v out(prog) = 1.0v) max1716-28 b 10a 0 20a 1.60v 1.65v 1.55v 1.50v a 40 s/div a. v out = 1.6v, 50mv/div b. i out = 0.3a to 18a, 10a/div circuit #4, v batt = 15v, pwm mode load-transient response with ceramic output capacitors max1716-29 typical operating characteristics (continued) (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.) b 10a 0 20a 1.55v 1.60v 1.50v a 40 s/div a. v out = 1.6v, 50mv/div; b. i out = 0.3a to 18a, 10a/div circuit #1, v batt = 15v, skip mode load-transient response (v batt = 15v, skip mode) max1716-26
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 11 5v 20 s/div 0 0 0 1v 2v 20a 10a a b c a. v out = 1.6v, 1v/div b. i l , l = 0.68 h, 10a/div c. short-circuit control, 5v/div short-circuit waveform max1716-30 b c 5v 200 s/div 0 0 0 1v 2v 20a 10a a a. v out = 1.6v, 1v/div b. i l , l = 0.68 h, 10a/div c. v shdn = 0 to v cc , 5v/div r out = 88m ? startup waveform (18a load) max1716-31 0 0 100 s/div 5v 5v 20a 0 2v 0 -20a a b c d a. v out = 1.6v, r out = 88m ? , 2v/div b. i l , l = 0.68 h, 20a/div c. v dl , 5v/div d. v shdn = v cc to 0, 5v/div shutdown waveform max1716-32 0 0 100 s/div 5v 5v 0 1v 2v 10a 0 a b c d a. v out = 1.6v, no load, 1v/div b. i l , l = 0.68 h, 10a/div c. v dl , 5v/div d. v shdn = 0 to v cc , 5v/div startup waveform (no-load) max1716-33 typical operating characteristics (continued) (circuit from figure 1, components from table 2, t a = +25 c, unless otherwise noted.)
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 12 ______________________________________________________________________________________ pin description pin name function 1 dh high-side gate driver output. dh swings from lx to bst. 2v+ battery voltage sense connection. connect v+ to input power source. v+ is used only for pwm one-shot timing. dh on-time is inversely proportional to input voltage over a 2v to 28v range. 3 shdn shutdown control input. drive shdn to gnd to force the max1716/MAX1854/max1855 into shutdown. drive or connect to v cc for normal operation. a rising edge on shdn clears the fault latch. 4fb feedback input. normally connected to v out . fb is connected to the bulk output filter capacitors locally at the power supply. an external resistive divider can optionally set the output voltage. 5cc voltage-positioning compensation capacitor. connect a 47pf to 1000pf (47pf typ) capacitor from cc to gnd to adjust the loop s response time. 6 ilim current-limit adjustment. the gnd-cs current-limit threshold defaults to 120mv, if ilim is tied to v cc . in adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ilim over a 0.5v to 2.0v range. the logic threshold for switchover to the 120mv default value is approximately v cc - 1v. connect ilim to ref for a fixed 200mv threshold. 7v cc analog supply input for pwm core. connect to the system supply voltage (+4.5v to +5.5v) with a series 20 ? resistor. bypass to gnd with a 0.22 f (min) ceramic capacitor. 8ton on-time selection-control input. this is a four-level input used to determine dh on-time. connect to gnd, ref, or v cc , or leave ton unconnected to set the following switching frequencies: gnd = 550khz, ref = 400khz, floating = 300khz, and v cc = 200khz. 9 ref +2.0v reference voltage output. bypass to gnd with 0.22 f (min) capacitor. can supply 50 a for external loads. 10 gnd analog gound 11 vps voltage-positioning sense input. connect to cs through a 1k ? resistor to maximize the load- dependent output voltage drop, or adjust the voltage positioning level by connecting a resistive divider from cs to pgnd. refer to setting voltage positioning on how to select resistor values. 12 vgate open-drain power-good output. vgate is normally high when the output is in regulation. vgate is low in shutdown, undervoltage lockout, and during soft-start. any fault condition forces vgate low, and it remains low until the fault is cleared. 13 dl low-side gate-driver output. dl swings from pgnd to v dd . 14 pgnd power ground 15 v dd supply input for the dl gate drive. connect to the system supply voltage, +4.5v to +5.5v. bypass to pgnd with a 1 f (min) ceramic capacitor. 16 d4 msb dac code input. 5 a internal pullup to v cc (table 5). 17 d3 dac code input. 5 a internal pullup to v cc (table 5). 18 d2 dac code input. 5 a internal pullup to v cc (table 5). 19 d1 dac code input. 5 a internal pullup to v cc (table 5). 20 d0 lsb dac code input. 5 a internal pullup to v cc (table 5).
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 13 pin description (continued) pin name function 21 skip pulse-skipping or low-noise mode control input. connect to v cc for low-noise forced-pwm mode. connect to gnd to enable pulse-skipping operation. low-noise forced-pwm mode causes inductor current recirculation at light loads and suppresses pulse-skipping operation. normal operation prevents current recirculation. skip can also be used to disable both overvoltage and undervoltage protection circuits and clear the fault latch (see no-fault test mode ). do not leave skip floating. 22 bst boost flying-capacitor connection. connect to an external capacitor and diode according to the standard application circuit (figure 1). 23 lx external inductor connection. connect lx to the switched side of the inductor. lx serves as the lower supply rail for the dh high-side gate driver. lx does not connect to the current-limit comparator. 24 cs current-sense input. connect a resistor (r sense ) between cs and pgnd. the current-limit threshold is set by ilim. if the current-sense signal (inductor current ? r sense ) exceeds the current-limit threshold, the max1716/MAX1854/max1855 will not initiate a new cycle. component circuit 1 (figure 1) circuit 2 (figure 11) circuit 3 (figure 12) circuit 4 (figure 13) output voltage 1.6v 1.3v 1.0v 1.6v input voltage range 7v to 24v 7v to 24v 7v to 24v 7v to 24v m axi m um load c ur r ent 18a 12a 12a 18a inductor 0.68 h sumida cdep134h-0r6 or panasonic etqp6f0r6bfa 1 h sumida cep125-1r0mc or panasonic etqp6firibfa 0.68 h sumida cdep134h-0r6 or panasonic etqp6f0r6bfa 0.47 h sumitomo cxe-r47 ton level float float ref gnd frequency 300khz 300khz 400khz 550khz high-side mosfet international rectifier (2) irf7811 international rectifier irf7811 international rectifier irf7811 international rectifier (2) irf7811 low-side mosfet fairchild (2) fds7764a or international rectifier (2) irf7811 fairchild (2) fds7764a or international rectifier (2) irf7811 fairchild (2) fds7764a or international rectifier (2) irf7811 fairchild (2) fds7764a or international rectifier (2) irf7811 input capacitor (5) 10 f taiyo yuden tmk432bj106 (4) 10 f taiyo yuden tmk432bj106 (4) 10 f taiyo yuden tmk432bj106 (5) 10 f taiyo yuden tmk432bj106 output capacitor (5) 220 f panasonic eefue0e221r (4) 220 f panasonic eefue0e221r (4) 220 f panasonic eefue0e221r (8) 47 f taiyo yuden jmk432bj476mm or tdk c4532x5roj476m current-sense resistor 3m ? 3.5m ? 3.5m ? 3m ? ilim level v ref /3 v ref /4 v ref /4 v ref /3 voltage-positioning resistor ratio 1:1 (0.5x) 1:2 (0.66x) 1:2 (0.66x) 1:1 (0.5x) table 1. component selection for standard applications
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 14 ______________________________________________________________________________________ _______________detailed description the max1716/MAX1854/max1855 buck controllers are targeted for low-voltage, high-current cpu core power supplies for notebook computers that typically require 18a (or greater) load steps. the proprietary quick- pwm pulse-width modulator in the converter is specifi- cally designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode pwms while also avoiding the problems caused by widely varying switching frequencies in con- ventional constant on-time and constant off-time pfm schemes. +5v bias supply (v cc and v dd ) the max1716/MAX1854/max1855 require an external +5v bias supply in addition to the battery. typically this +5v bias supply is the notebook s 95% efficient +5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associat- ed with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v supply can be generated with an external linear regulator. the +5v bias supply powers v cc (pwm controller) and v dd (gate-drive power). the maximum current is: i bias = i cc + ? (q g1 + q g2 ) = 10ma to 40ma (typ) where i cc is 700a (typ), ? is the switching frequency, and q g1 and q g2 are the mosfet data sheet total gate-charge specification limits at v gs = 5v. the battery input (v+) and +5v bias inputs (v cc and v dd ) can be connected together if the input source is a fixed 4.5v to 5.5v supply. if the +5v bias supply is powered up prior to the battery supply, the enable sig- nal ( shdn ) must be delayed until the battery voltage is present to ensure startup. free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a constant-on- time, current-mode type with voltage feed-forward (figure 2). this architecture relies on the output ripple voltage to provide the pwm ramp signal. thus, the out- put filter capacitor s esr acts as a feedback resistor. the control algorithm is simple: the high-side switch on- time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly pro- portional to output voltage (see on-time one-shot ). another one-shot sets a minimum off-time (400ns typ). the on-time one-shot is triggered if the error compara- manufacturer phone (country code) website mosfets fairchild semiconductor (1) 888-522-5372 www.fairchildsemi.com international rectifier (1) 310-322-3331 www.irf.com siliconix (1) 203-268-6261 www.vishay.com capacitors kemet (1) 408-986-0424 www.kemet.com panasonic (1) 847-468-5624 www.panasonic.com sanyo (65) 281-3226 (singapore) (1) 408-749-9714 www.secc.co.jp taiyo yuden (03) 3667-3408 (japan) (1) 408-573-4150 www.t-yuden.com tdk (1) 847-390-4373 www.tdk.com inductors coilcraft (1) 800-322-2645 www.coilcraft.com coiltronics (1) 561-752-5000 www.coiltronics.com sumida (1) 408-982-9660 www.sumida.com sumitomo (1) 408-451-8441 (usa) 81 75 961-3141 (japan) www.ssmc.co.jp table 2. component suppliers
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 15 tor is low, the low-side switch current is below the cur- rent-limit threshold, and the minimum off-time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to the input and output voltages. the high- side switch on-time is inversely proportional to v+, and directly proportional to the output voltage as set by the dac code. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequen- cy clock generator. the benefits of a constant switch- ing frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions, such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output volt- age ripple. on-time = k (v out + 75mv) / v+ where k is set by the ton pin-strap connection, and 75mv is an approximation to accommodate for the expected drop across the low-side mosfet switch and current-sense resistor (table 3). the on-time one-shot has good accuracy at the operat- ing points specified in the electrical characteristics table. on-times at operating points far removed from the conditions specified in the electrical characteristics table can vary over a wide range. for example, the 550khz setting will typically run about 10% slower with inputs much greater than the +5v due to the very short on-times required. while the on-time is set by ton, v+, and the output voltage, other factors also contribute to the overall v cc c out (5) 220 f panasonic d2 l1 0.68 h 1.6v output up to 18a shdn vgate d1 c4 1 f c3 0.1 f q1 q2 c5 1 f r3 10 ? c in (5) 10 f battery (v batt ) 7v to 24v ref ilim cc +5v input bias supply power-good indicator dl lx v+ dh bst cs pgnd vps fb ton v dd max1716 MAX1854 max1855 skip d0 d1 d2 d3 d4 gnd r6 100k ? to v cc r4 100k ? r5 200k ? c2 47pf c1 0.22 f on off r2 1k ? float (300khz) max1716 dac code shown r1 1k ? r sense 3m ? q1: (2) irf7811 international rectifier q2: (2) irf7811 international rectifier d1: cmpsh-3 central semiconductor d2: cmsh2-60 central semiconductor figure 1. standard high-power application (circuit #1)
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 16 ______________________________________________________________________________________ figure 2. functional diagram ref -10% from out ref 7r r d0 error amp toff ton ref +10% chip supply x2 shdn vps cc vgate * no overvoltage protection on the MAX1854 d1 d2 d3 d4 on-time compute ton 1-shot 1-shot trig in 2v to 28v trig q q s r 2v ref r-2r dac ref ref pgnd +5v output cs dl cs v cc v dd lx zero crossing current limit dh bst 9r r i lim +5v +5v q skip ton v+ max1716 MAX1854 max1855 s r q ovp/uvp detect * 200k gm fb ton setting (khz) k-factor ( s) approximate k-factor error (%) min recommended v batt at v out = 1.6v (v) 200 5 9 2.04 300 3.3 11 2.28 400 2.2 15 2.84 550 1.8 20 3.55 table 3. approximate k-factor errors
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 17 switching frequency. the on-time guaranteed in the electrical characteristics table is influenced by switch- ing delays in the external high-side mosfet. resistive losses including the inductor, both mosfets, output capacitor esr, and pc board copper losses in the out- put and ground tend to raise the switching frequency at higher output currents. switch dead-time can increase the effective on-time, reducing the switching frequency. this effect occurs only in pwm mode ( skip = high) when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor s emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead-time. when the controller operates in continuous mode, the dead-time is no longer a factor and the actual switching frequency is: ? = (v out + v drop1 ) / [t on (v+ + v drop1 v drop2 )] where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, includ- ing high-side switch, inductor, and pc board resis- tances; and t on is the on-time calculated by the max1716/MAX1854/max1855. automatic pulse-skipping switchover in skip mode ( skip = low), an inherent automatic switchover to pfm takes place at light loads (figure 3). this switchover is controlled by a comparator that trun- cates the low-side switch on-time at the inductor cur- rent s zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskip- ping pwm operation to coincide with the boundary between continuous and discontinuous inductor-cur- rent operation. for an input voltage (v+) range of 7v to 24v, this threshold is relatively constant, with only a minor dependence on the input voltage: where k is the on-time scale factor (table 3). the load- current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple cur- rent, which is a function of the inductor value (figure 3). for example, in the standard application circuit with k = 3.3s (300khz), v batt = 12v, v out = 1.6v, and l = 0.68h, switchover to pulse-skipping operation occurs at i load = 2.3a or about 1/4 full load. the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation; this is a normal operating condition that improves light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the induc- tor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input voltage levels). forced-pwm mode ( s s k k i i p p = high) the low-noise, forced-pwm mode ( skip driven high) disables the zero-crossing comparator that controls the inductor current i limit i load 0 time -i peak figure 4. valley current-limit threshold point inductor current i load = i peak /2 on-time 0 time -i peak l v batt - v out ? i ? t = figure 3. pulse-skipping/discontinuous crossover point i kv l vv v load skip out out () ? ? ? ? ? ? +? + ? ? ? ? ? ? 2
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 18 ______________________________________________________________________________________ low-side switch on-time. the resulting low-side gate- drive waveform is forced to be the complement of the high-side gate-drive waveform. this, in turn causes the inductor current to reverse at light loads, as the pwm loop strives to maintain a duty ratio of v out /v+. the benefit of forced-pwm mode is to keep the switching frequency nearly constant, but it results in higher no- load supply current that can be 10ma to 40ma, depending on the external mosfets and switching fre- quency. forced-pwm mode is most useful for minimizing audio- frequency noise and improving the cross-regulation of multiple-output applications that use a flyback trans- former or coupled inductor. current-limit circuit (ilim) the current-limit circuit employs a unique valley cur- rent-sensing algorithm. if the current-sense signal is above the current-limit threshold, the max1716/ MAX1854/max1855 will not initiate a new cycle (figure 4). the actual peak current is greater than the current- limit threshold by an amount equal to the inductor rip- ple current. therefore, the exact current-limit characteristic and maximum load capability are a func- tion of the current-limit threshold, inductor value, and input voltage. the reward for this uncertainty is robust, loss-less overcurrent sensing. when combined with the uvp protection circuit, this current-limit method is effec- tive in almost every circumstance. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sink- ing current. the negative current-limit threshold is set to approximately 120% of the positive current limit and therefore tracks the positive current limit when ilim is adjusted. the max1716/MAX1854/max1855 measure the current by sensing the voltage between cs and pgnd. connect an external sense resistor between the source of the low-side n-channel mosfet and pgnd. this same resistor is also used to generate the input voltage for the vps input (see setting voltage positioning ). reducing the sense voltage increases the relative mea- surement error. however, the configuration eliminates the uncertainty of using the low-side mosfet on-resis- tance to measure the current, so the resulting current- limit tolerance is tighter when sensing with a 1% sense resistor. in some applications, the signal required for voltage positioning is much smaller than the minimum current- limit voltage (50mv). there are two options for address- ing this issue. one method is to use a larger current-sense resistor to develop the appropriate cur- rent-limit voltage and divide down this signal to obtain the desired vps input. this solution provides the maxi- mum current-limit accuracy. alternatively, select a sense resistance to generate the desired vps voltage and connect cs to lx. this results in minimum power- dissipation with reduced current-limit accuracy. the default 120mv current limit (ilim = v cc ) accommo- dates current-limit detection using the low-side power mosfet and low-value sense resistor. the voltage at ilim sets the current-limit threshold. for voltages from 500mv to 2v, the current-limit threshold voltage is precisely 0.1 v ilim . set this voltage with a resistive divider between ref and gnd. the current- limit threshold defaults to 120mv when ilim is tied to shdn skip dl mode comments 0 x high shutdown micropower shutdown state. 1 gnd switching normal operation automatic switchover from pwm mode to pulse-skipping pfm mode at light loads. prevents inductor current from recirculating into the input. 1v cc switching forced pwm low-noise forced-pwm mode causes inductor current to reverse at light loads and suppresses pulse-skipping operation. 1 below gnd switching no-fault test mode test mode with overvoltage, undervoltage, and thermal shutdown faults disabled. otherwise, the converter operates as if skip = gnd. x = don t care table 4. operating mode truth table
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 19 v cc . the logic threshold for switchover to the 120mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors don t corrupt the cur- rent-sense signals seen by cs and pgnd. the ic must be mounted close to the current-sense resistor with short, direct traces making a kelvin sense connection. mosfet gate drivers (dh and dl) the dh and dl drivers are optimized for driving mod- erate-sized, high-side and larger, low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v in - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high- side fet from turning on until dl is fully off. there must be a low-resistance, low-inductance path from the dl driver to the mosfet gate in order for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the max1716/MAX1854/max1855 will interpret the mosfet gate as off while there is actual- ly still charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the mosfet is 1 inch from the device). the dead time at the other edge (dh turning off) is determined by a fixed 35ns internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.5 ? (typ) on-resistance. this helps pre- vent dl from being pulled up during the fast rise time of the lx node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfet. however, for high-current applications, some combinations of high- and low-side fets may cause excessive gate-drain coupling, leading to poor efficien- cy, emi, and shoot-through currents. this is often reme- died by adding a resistor in series with bst, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 5). dac converter (d0?4) the digital-to-analog converter (dac) programs the output voltage. it receives a preset digital code from the vid inputs (d0 d4), which contain weak internal pullups to eliminate external resistors. they can also be driven by digital logic, general-purpose i/o, or an exter- nal multiplexer. the available dac codes and resulting output voltages (table 5) are compatible with intel s mobile pentium iii specifications. d0-d4 can be changed while the regulator is active, ini- tiating a transition to a new output voltage level. change d0 d4 synchronously to avoid errors during a v out transition. if the skew between bits exceeds 1s, incorrect dac outputs may cause a partial transition to the wrong voltage level, followed by the intended tran- sition to the correct voltage level, lengthening the over- all transition time. when changing the max1855 dac code while pow- ered up, the undervoltage protection feature can be activated if the code change increases the output volt- age by more than 120%. for example, a transition from any dac code below 0.8v to 1.75v will activate the undervoltage protection. in the preceding example, transitioning from 0.8v to 1.35v and then from 1.35v to 1.75v avoids activating the undervoltage protection feature. shutdown ( s s h h d d n n ) drive shdn low to force the max1716/MAX1854/ max1855 into a low-current shutdown state. shutdown turns on the low-side mosfet by forcing the dl gate driver high, which discharges the output capacitor and forces the output to ground. drive or connect shdn to v cc for normal operation. a rising edge on shdn clears the fault latch. power-on reset power-on reset (por) occurs when v cc rises above approximately 2v. this resets the fault latch and soft- start counter, preparing the regulator for operation. bst +5v v batt 5 ? typ dh lx max1716 MAX1854 max1855 figure 5. reducing the switching-node rise time pentium iii is a trademark of intel corp.
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 20 ______________________________________________________________________________________ undervoltage lockout and soft-start v cc undervoltage lockout (uvlo) circuitry inhibits switching, forces vgate low, and drives the dl output high. if the v cc voltage drops below 4.2v, it is assumed that there is not enough supply voltage to make valid decisions. to protect the output from over- voltage faults, dl is forced high in this mode. this will force the output to gnd and results in large negative inductor current that pulls the output below gnd. if v cc is likely to drop in this fashion, the output can be output voltage d4 d3 d2 d1 d0 max1716 MAX1854 max1855 00000 no cpu* 2.000v 1.750v 00001 no cpu* 1.950v 1.700v 00010 no cpu* 1.900v 1.650v 00011 no cpu* 1.850v 1.600v 00100 no cpu* 1.800v 1.550v 00101 no cpu* 1.750v 1.500v 00110 no cpu* 1.700v 1.450v 00111 no cpu* 1.650v 1.400v 01000 1.600v 1.600v 1.350v 01001 1.550v 1.550v 1.300v 01010 1.500v 1.500v 1.250v 01011 1.450v 1.450v 1.200v 01100 1.400v 1.400v 1.150v 01101 1.350v 1.350v 1.100v 01110 1.300v 1.300v 1.050v 01111 no cpu* no cpu* 1.000v 10000 1.275v 1.275v 0.975v 10001 1.250v 1.250v 0.950v 10010 1.225v 1.225v 0.925v 10011 1.200v 1.200v 0.900v 10100 1.175v 1.175v 0.875v 10101 1.150v 1.150v 0.850v 10110 1.125v 1.125v 0.825v 10111 1.100v 1.100v 0.800v 11000 1.075v 1.075v 0.775v 11001 1.050v 1.050v 0.750v 11010 1.025v 1.025v 0.725v 11011 1.000v 1.000v 0.700v 11100 0.975v 0.975v 0.675v 11101 0.950v 0.950v 0.650v 11110 0.925v 0.925v 0.625v 11111 no cpu* no cpu* 0.600v * note: in the no-cpu state, dh and dl are held low. table 5. output voltage vs. dac codes
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 21 clamped with a schottky diode to gnd to reduce the negative excursion. to ensure correct startup, v+ should be present before v cc . if the converter attempts to bring the output into regulation without v+ present, the fault latch will trip. after v cc rises above 4.2v, an internal digital soft-start timer begins to ramp up the maximum allowed current limit. the ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%, with 100% load current available after 1.7ms 50%. power-good output (vgate) vgate is the open-drain output of a window compara- tor. this power-good output remains high impedance as long as the output voltage is within 10% of the reg- ulation voltage. when the output voltage is greater than or less than the 10% window limits, the internal mos- fet is activated and pulls the output low. any fault con- dition forces vgate low until the fault is cleared. vgate is also low in shutdown, undervoltage lockout, and during soft-start. for logic-level output voltages, connect an external pullup resistor between vgate and v cc (or v dd ). a 100k ? resistor works well in most applications. output overvoltage protection (max1716/max1855 only) the overvoltage protection (ovp) circuit is designed to protect against a shorted high-side mosfet by draw- ing high current and activating the battery s protection circuit. the output voltage is continuously monitored for overvoltage. if the output exceeds the ovp threshold (1.9v with the max1716, 2.0v with the max1855), ovp is triggered and the circuit shuts down. the dl low- side gate-driver output latches high until shdn toggles or v cc pulses below 1v. this action turns on the syn- chronous-rectifier mosfet with 100% duty cycle and, in turn, rapidly discharges the output filter capacitor, forcing the output to ground. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery s internal protection cir- cuit will engage. ovp can be defeated through the no-fault test mode (see no-fault test mode ). output undervoltage protection the output undervoltage protection (uvp) function is similar to foldback current limiting, but employs a timer rather than a variable current limit. if the regulator s out- put voltage is under 40% of the nominal value, anytime after the 20ms undervoltage fault-blanking time, the pwm is latched off and won t restart until shdn toggles or v cc pulses below 1v. uvp can be defeated through the no-fault test mode (see no-fault test mode ). thermal fault protection the max1716/MAX1854/max1855 feature a thermal fault protection circuit. when the temperature rises above +150 c, the dl low-side gate-driver output latches high until shdn toggles or v cc pulses below 1v. the threshold has +10 c of thermal hysteresis, which prevents the regulator from restarting until the die cools off. no-fault test mode the over/undervoltage protection features can compli- cate the process of debugging prototype breadboards since there are at most a few milliseconds in which to determine what went wrong. therefore, a test mode is provided to disable the ovp, uvp, and thermal shut- down features, and clear the fault latch if it has been set. the pwm operates as if skip were low (skip mode). the no-fault test mode is entered by sinking 1.5ma from skip through an external negative voltage source in series with a resistor. skip is clamped to gnd with a silicon diode, so choose the resistor value equal to (v force - 0.65v) / 1.5ma. design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point. the follow- ing four factors dictate the design: input voltage range: the maximum value (v+ (max) ) must accommodate the worst-case high ac-adapter voltage. the minimum value (v+ (min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus dri- ves the selection of input capacitors, mosfets, and other critical heat-contributing components. modern notebook cpus generally exhibit i load = i load(max) 80%. switching frequency: this choice determines the basic trade-off between size and efficiency. the opti-
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 22 ______________________________________________________________________________________ mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are pro- portional to frequency and v+ 2 . the optimum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequen- cies more practical. inductor operating point: this choice provides trade- offs between size vs. efficiency. low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the max1716/MAX1854/max1855 s pulse-skipping algorithm initiates skip mode at the critical-conduction point. thus, the inductor operating point also deter- mines the load-current value at which pfm/pwm switchover occurs. the optimum point is usually found between 20% and 50% ripple current. the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time: where t off(min) is the minimum off-time (see electrical characteristics ), and k is from table 3. inductor selection the switching frequency and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) = 18a, v in = 7v, v out = 1.6v, f sw = 300khz, 30% ripple current or lir = 0.3. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (ipeak). i peak = i load(max) + (i load(max) lir / 2) setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: i limit(low) > i load(max) - (i load(max) lir / 2) where i limit(low) equals the minimum current-limit threshold voltage divided by r sense . for the 120mv default setting, the minimum current-limit threshold is 110mv. connect ilim to v cc for a default 120mv current-limit threshold. in the adjustable mode, the current-limit threshold is precisely 1/10th the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to gnd, with ilim connected to the center tap. the external 0.5v to 2.0v adjustment range corre- sponds to a current-limit threshold of 50mv to 200mv. when adjusting the current limit, use 1% tolerance resistors and a 10a divider current to prevent a signifi- cant increase of errors in the current-limit value. output capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition with- out tripping the overvoltage protection circuit. in cpu v core converters and other applications where the output is subject to violent load transients, the out- put capacitor s size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: r esr = v step(max) / i load(max) the actual f capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, and other electrolytics). l vv v v khz a h = ? = 16 7 16 7 300 0 30 18 076 .( .) . . l vvv v lir i out out sw load max = +? () + ? () v ii lk v v t cvk vv v t sag load load out off min out out out off min = ? + ? ? ? ? ? ? ? ? ? ? ? ? ? +? + ? ? ? ? ? ? ? ? ? ? ? ? ? () () () 12 2 2
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 23 when using low-capacity filter capacitors, such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent v sag, and v soar from causing problems during load tran- sients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag equation in the design procedure) . the amount of over- shoot due to stored inductor energy can be calculated as: v soar (l i peak 2 ) / (2 c out v out ) where i peak is the peak inductor current. output capacitor stability considerations stability is determined by the value of the esr zero rel- ative to the switching frequency. the boundary of insta- bility is given by the following equation: ? esr = ? sw / where: ? esr = 1 / (2 r esr c out ) for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in widespread use at the time of this publi- cation have typical esr zero frequencies below 30khz. in the standard application used for inductor selection, the esr needed to support a 50mvp-p ripple is 50mv/(18a 0.3) = 9.3m ? . five 220f/2.5v panasonic sp capacitors in parallel provide 3m ? (max) esr. their typical combined esr results in a zero at 48khz. don t put high-value ceramic capacitors directly across the output without taking precautions to ensure stability. ceramic capacitors have a high esr zero frequency and may cause erratic, unstable operation. however, it s easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and fb pin. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feed- back loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there isn t enough volt- age ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immedi- ately after the minimum off-time period has expired. double-pulsing is more annoying than harmful, result- ing in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can cause the out- put voltage to rise above or fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. don t allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple-current requirement (i rms ) imposed by the switching currents defined by the following equation: for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the max1716/MAX1854/max1855 are operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits <+10 c temperature rise at the rms input cur- rent for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>18a) when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. for maximum efficiency, choose a high-side mosfet that has conduction losses equal to the switching loss- es at the average input voltage (3 li+ cells = 11v, 4 li+ cells = 14v). check to ensure that conduction losses plus switching losses don t exceed the package ratings or violate the overall thermal budget at the maximum and minimum input voltages. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., one or two so-8s, dpak or d 2 pak), and is reasonably priced. make sure that the dl gate driver can supply sufficient current to support the gate charge and the current injected into the para- sitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems may occur. ii vvv v rms load out out = +? () +
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 24 ______________________________________________________________________________________ mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (q1), the worst- case power dissipation due to resistance occurs at the minimum input voltage: pd (q1 resistive) = (v out /v+) i load 2 r ds(on) generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses don t usually become an issue until the input is greater than approximately 15v. calculating the power dissipation in the high-side mos- fet (q1) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold volt- age, source inductance, and pc board layout charac- teristics. the following switching-loss calculation provides only a very rough estimate and is no substi- tute for breadboard evaluation, preferably including verification using a thermocouple mounted on q1: where c rss is the reverse transfer capacitance of q1, and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c v 2 sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from v+ (max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (q2), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, overdesign the circuit to tolerate: i load = i limit(high) + (i load(max) lir/2) where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must be very well heatsinked to handle the overload power dissipation. choose a schottky diode (d1) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead-time. as a gen- eral rule, select a diode with a dc current rating equal to 1/3 of the load current. this diode is optional and can be removed if efficiency isn t critical. setting voltage positioning (vps) voltage positioning dynamically changes the output voltage set point in response to the load current. when the output is loaded, the signal fed back from the vps input adjusts the output voltage set point, thereby decreasing power dissipation. the load transient response of this control loop is extremely fast yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. to under- stand the benefits of dynamically adjusting the output voltage, see voltage positioning and effective efficiency . the amount of voltage change is set by a small-value sense resistor (r sense ). place this resistor between the source of the low-side mosfet and pgnd. the volt- age developed across this resistor (v vps ) relates to the output voltage as follows: v out = v out(prog) (1 + a vps v vps ) where v out(prog) is the programmed output voltage set by the dac code (table 5), and the voltage-posi- tioning gain factor (a vps ) is 0.175%/mv (see electrical characteristics ). the max1716/MAX1854/max1855 contain internal clamps to limit the voltage positioning between 10% below and 2% above the programmed output voltage. the voltage present at vps can be set in several differ- ent ways. connect vps directly to cs through a 1k ? resistor, or through a resistive divider. when connected directly to cs, the output voltage position is: v vps = v cs = -i load r sense (1 - d) where d = v out / v+ is the regulator s duty cycle. however, since the ratio of the output to input voltage is usually relatively large, the effect of the duty cycle on the circuit s performance is not significant. therefore, pd (q2 resistive) i v out v (max) i load 2 r ds (on) =? + ? ? ? ? ? ? ? ? pd (q1 switching) c rss v (max) 2 f sw i load i gate = +
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 25 the complete expression for the voltage-positioned out- put depends only upon the value of the current-sense resistor and the load current: v out v out(prog) (1 - a vps i load r sense ) some applications require the addition of a positive off- set to the output voltage to ensure that it remains within the load specifications. the positive offset may be gen- erated by connecting a resistive divider from ref to vps to cs (figure 6a). set r1 to 1k ? , and use the fol- lowing equation to calculate r3: where v ref is typically 2.0v, and v offset is the required positive offset voltage. when attenuating the voltage-positioning signal, replace r1 with the parallel combination of r1 and r2 (r1//r2), where r2 is the attenuation resistor (figure 6b). after a load transient, the output instantly changes by esr cout ? i load . setting the load-dependent volt- age position to match this initial load step allows the output voltage to change by esr cout ? i load and stay there as long as the load remains unchanged (see voltage positioning and effective efficiency ). to set the voltage position equal to the initial voltage drop gener- ated by the output capacitor s esr, select r sense = esr cout / (v out(prog) a vps ). for applications using a larger current-sense resistor, adjust v vps by connecting a resistive divider from cs to vps to pgnd (figure 6b). set r1 to 1k ? , and use the following equation to calculate r2: the max1716/MAX1854/max1855 voltage-positioning circuit has several advantages over older circuits, which added a fixed voltage offset on the sense point and used a low-value resistor in series with the output. the new circuit can use the same current-sense resis- tor for both voltage positioning and current-limit detec- tion. this simultaneously provides accurate current limiting and voltage positioning. since the new circuit adjusts the output voltage within the control loop, the voltage-positioning signal may be internally amplified. the additional gain allows the use of low-value current- sense resistors, so the power dissipated in this sense resistor is significantly lower than a single resistor con- nected directly in series with the output. voltage-positioning compensation (cc) the voltage-positioning compensation capacitor filters the amplified vps signal, allowing the user to adjust the dynamics of the voltage-positioning loop. the imped- ance at this node is approximately 200k ? , so the pole provided by this node can be approximated by 1 / (2 rc). the response time is set with a 47pf to 1000pf capacitor from cc to gnd. rr esr a v r esr cout vps out prog sense cout 21 = ? ? ? ? ? ? ? ? ? () rr va v v ref vps out prog offset 31 1 =? ? ? ? ? ? ? () max1716 MAX1854 max1855 dl cs vps pgnd n r1 r sense a) scaled voltage position signal b) positive no-load voltage positioning r2 max1716 MAX1854 max1855 ref vps cs dl pgnd r3 q2 r1 r sense c ref 0.22 f figure 6. voltage-positioning configurations
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 26 ______________________________________________________________________________________ ________________applications issues voltage positioning and effective efficiency powering new mobile processors requires careful attention to detail to reduce cost, size, and power dissi- pation. as cpus became more power hungry, it was recognized that even the fastest dc-dc converters were inadequate to handle the transient power require- ments. after a load transient, the output instantly changes by esr cout ? i load . conventional dc-dc converters respond by regulating the output voltage back to its nominal state after the load transient occurs (figure 7). however, the cpu only requires that the out- put voltage remain above a specified minimum value. dynamically positioning the output voltage to this lower limit allows the use of fewer output capacitors and reduces power consumption under load. for a conventional (nonvoltage-positioned) circuit, the total voltage change is: v p-p1 = 2 (esr cout ? i load ) + v sag + v soar where v sag and v soar are defined in figure 8. setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output cur- rent suddenly decreases (figure 7). so the total voltage change for a voltage positioned circuit is: v p-p2 = (esr cout ? i load ) + v sag + v soar where v sag and v soar are defined in the design procedure. since the amplitudes are the same for both circuits (v p-p1 = v p-p2 ), the voltage-positioned circuit requires only twice the esr. since the esr specifica- tion is achieved by paralleling several capacitors, fewer units are needed for the voltage-positioned circuit. an additional benefit of voltage positioning is reduced power consumption at high load currents. because the output voltage is lower under load, the cpu draws less current. the result is lower power dissipation in the cpu, although some extra power is dissipated in r sense . for a nominal 1.6v, 18a output (r load = 89m ? ), reducing the output voltage 2.9% gives an out- put voltage of 1.55v and an output current of 17.44a. given these values, cpu power consumption is reduced from 28.8w to 27.03w. the additional power consumption of r sense is: 2.5m ? (17.44a) 2 = 0.76w and the overall power savings is as follows: 28.8w - (27.03w + 0.76w) = 1.01w in effect, 1.8w of cpu dissipation is saved and the power supply dissipates much of the savings, but both the net savings and the transfer of heat away from the cpu are beneficial. effective efficiency is defined as the efficiency required of a nonvoltage-positioned cir- cuit to equal the total dissipation of a voltage-posi- tioned circuit for a given cpu operating condition. calculate effective efficiency as follows: 1) start with the efficiency data for the positioned circuit (v in , i in , v out , i out ). 2) model the load resistance for each data point: i load capacitor soar (energy in l transferred to c out ) capacitive sag (dv/dt = i out /c out ) recovery esr step-down and step-up (i step x esr) v out figure 8. transient-response regions b 1.6v 1.6v a a. conventional converter (50mv/div) b. voltage positioned output (50mv/div) voltage positioning the output max1716-figure 07 figure 7. voltage positioning the output
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 27 r load = v out / i out 3) calculate the output current that would exist for each r load data point in a nonpositioned application: i np = v np / r load where v np = 1.6v (in this example). 4) calculate effective efficiency as: effective efficiency = (v np i np ) / (v in i in ) = calculated nonpositioned power output divided by the measured voltage-positioned power input. 5) plot the efficiency data point at the nonpositioned current, i np . the effective efficiency of voltage-positioned circuits is shown in the typical operating characteristics . dropout performance the output-voltage adjustable range for continuous- conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. for best dropout performance, use the slower (200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the ton k-factor. this error is greater at higher fre- quencies (table 3). also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down is an indicator of ability to slew the inductor current higher in response to increased load and must always be >1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see on-time one-sho t), t off(min) is from the electrical characteristics table, and k is taken from table 3. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then reduce the operating fre- quency or add output capacitance to obtain an accept- able v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient re- sponse. dropout design example: v out = 1.6v ? sw = 550khz k = 1.8s, worst-case k = 1.58s t off(min) = 500ns v drop1 = v drop2 = 100mv h = 1.5 v in(min) = [(1.6v + 0.1v) / (1 - (0.5s 1.5 / 1.58s))] + 0.1v - 0.1v = 3.2v calculating again with h = 1 gives the absolute limit of dropout: v in(min) = [(1.6v + 0.1v) / (1 - (0.5s 1.0 / 1.58s))] + 0.1v - 0.1v = 2.5v therefore, v in must be greater than 2.5v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.2v. adjusting v out with a resistive divider the output voltage can be adjusted with a resistive- divider rather than the dac if desired (figure 9). the drawback is that the on-time doesn t automatically receive correct compensation for changing output volt- age levels. this can result in variable switching fre- quency as the resistor ratio is changed, and/or excessive switching frequency. the equation for adjust- ing the output voltage is: v out = v fb (1 + r1 / (r2 || r int )) where v fb is the currently selected dac value, and r int is the fb input resistance. in resistor-adjusted cir- cuits, the dac code should be set as close as possible to the actual output voltage in order to minimize the shift in switching frequency. adjusting v out above 2v the feed-forward circuit that makes the on-time depen- dent on the input voltage maintains a nearly constant switching frequency as v+, i load , and the dac code are changed. this works extremely well as long as fb is connected directly to the output. when the output is v in(min) = 1 k v out + v drop1 + v drop2 v drop1 t off(min) h
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 28 ______________________________________________________________________________________ adjusted with a resistor-divider, the switching frequen- cy is increased by the inverse of the divider ratio. this change in frequency can be compensated with the addition of a resistor-divider to the battery-sense input (v+). attach a resistor-divider from the battery voltage to v+ on the max1716/MAX1854/max1855, with the same attenuation factor as the output divider. the v+ input has a nominal input impedance of 600k ? , which should be considered when selecting resistor values. one-stage (battery input) vs. two-stage (5v input) applications the max1716/MAX1854/max1855 can be used with a direct battery connection (one stage) or can obtain power from a regulated 5v supply (two stage). each approach has advantages, and careful consideration should go into the selection of the final design. the one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5v supply. the transient response of the single stage is better due to the ability to ramp the inductor current faster. the total efficiency of a single stage is better than the two-stage approach. the two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipa- tion. the power supply can be placed closer to the cpu for better regulation and lower i 2 r losses from pc board traces. although the two-stage design has slow- er transient response than the single stage, this can be offset by the use of a voltage-positioned converter. ceramic output capacitor applications ceramic capacitors have advantages and disadvan- tages. they have ultra-low esr and are noncom- bustible, relatively small, and nonpolarized. however, they are also expensive and brittle, and their ultra-low esr characteristic can result in excessively high esr zero frequencies. in addition, their relatively low capac- itance value can cause output overshoot when step- ping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored inductor energy. in some cases, there may be no room for electrolytics, creating a need for a dc-dc design that uses nothing but ceramics. the max1716 can take full advantage of the small size and low esr of ceramic output capacitors in a voltage- positioned circuit. the addition of the positioning resis- tor increases the ripple at fb, lowering the effective esr zero frequency of the ceramic output capacitor. output overshoot (v soar) determines the minimum out- put capacitance requirement (see output capacitor selection ). often the switching frequency is increased to 400khz or 550khz, and the inductor value is reduced to minimize the energy transferred from induc- tor to capacitor during load-step recovery. the efficien- cy penalty for operating at 400khz is about 2% to 3% and about 5% at 550khz when compared to the 300khz voltage-positioned circuit, primarily due to the high-side mosfet switching losses. table 1 and the typical operating characteristics include a circuit using ceramic capacitors with a 550khz switching frequency (figure 13). pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 10). if possible, mount all of the power compo- nents on the top side of the board with their ground ter- minals flush against one another. follow these guidelines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. 2) connect all analog grounds to a separate solid cop- per plane, which connects to the gnd pin of the max1716/MAX1854/max1855. this includes the max1716 MAX1854 max1855 dh lx cs vps dl pgnd fb v out q2 q1 r4 r5 l1 r sense v out = v fb (1 + r4/r5) figure 9. adjusting v out with a resistor-divider
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 29 v cc , ref, and cc capacitors, as well as the resis- tive-dividers connected to fb and ilim. 3) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance caus- es a measurable efficiency penalty. 4) cs and pgnd connections for current limiting must be made using kelvin sense connections to guaran- tee the current-limit accuracy. 5) when trade-offs in trace lengths must be made, it s preferable to allow the inductor charging path to be made longer than the discharge path. for example, it s better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low-side mosfet or between the inductor and the output filter capacitor. 6) ensure the fb connection to the output is short and direct. 7) route high-speed switching nodes away from sensi- tive analog areas (cc, ref, ilim). make all pin-strap control input connections (skip, shdn , ilim, etc.) to analog ground or v cc rather than pgnd or v dd . layout procedure 1) place the power components first, with ground termi- nals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connec- tions on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate trace must be short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the mosfet is 1 inch from the controller ic). d1 d1 via to v+ via to lx via to fb via to source of q2 via to gnd near r sense via to cs and vps inductor discharge path has low dc resistance. v dd all analog grounds connect to local plane only notes: "star" ground is used. d1 is directly across q2. connect local analog ground plane directly to gnd from the side opposite the v dd capacitor gnd to avoid v dd ground currents from flowing in the analog ground plane. max1717 battery input l1 v out q2 q1 r sense d1 gnd input gnd output gnd v cc cc ref c out c in figure 10. power-stage pc board layout example
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 30 ______________________________________________________________________________________ 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 1. this diagram can be viewed as having three separate ground planes: output ground, where all the high-power components go; the gnd plane, where the gnd pin and v dd bypass capaci- tors go; and an analog ground plane where sensitive analog components go. the analog ground plane and gnd plane must meet only at a single point directly beneath the ic. these two planes are then connected to the high-power output ground with a short connection from gnd to the source of the low- side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. ___________________chip information transistor count: 3729 v cc c out (4) 220 f d2 l1 1.0 h 1.3v output up to 12a shdn vgate d1 c4 1 f c3 0.1 f q1 q2 c5 1 f r3 10 ? c in (4) 10 f battery (v batt ) 7v to 24v ref ilim cc +5v input bias supply power-good indicator dl lx v+ dh bst cs pgnd vps fb ton v dd max1716 MAX1854 max1855 skip d0 d1 d2 d3 d4 gnd r6 100k ? to v cc r4 100k ? r5 300k ? c2 47pf c1 0.22 f on off r2 2k ? float (300khz) r1 1k ? r sense 3.5m ? q1: irf7811 international rectifier q2: (2) irf7811 international rectifier d1: cmpsh-3 central semiconductor d2: cmsh2-60 central semiconductor max1716 dac code shown figure 11. low-current application (circuit #2)
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning ______________________________________________________________________________________ 31 v cc c out (4) 220 f d2 l1 0.68 h 1.0v output up to 12a shdn vgate d1 c4 1 f c3 0.1 f q1 q2 c5 1 f r3 10 ? c in (4) 10 f battery (v batt ) 7v to 24v ref ilim cc +5v input bias supply power-good indicator dl lx v+ dh bst cs pgnd vps fb ton v dd max1716 MAX1854 max1855 skip d0 d1 d2 d3 d4 gnd r6 100k ? to v cc r4 100k ? r5 300k ? c2 47pf c1 0.22 f on off r2 2k ? ref (400khz) r1 1k ? r sense 3.5m ? q1: irf7811 international rectifier q2: (2) irf7811 international rectifier d1: cmpsh-3 central semiconductor d2: cmsh2-60 central semiconductor max1716 dac code shown figure 12. low-voltage application (circuit #3)
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning 32 ______________________________________________________________________________________ v cc c out (8) 47 f d2 l1 0.47 h 1.6v output up to 18a shdn vgate d1 c4 1 f c3 0.1 f q1 q2 c5 1 f r3 10 ? c in (5) 10 f battery (v batt ) 7v to 24v ref ilim cc +5v input bias supply power-good indicator dl lx v+ dh bst cs pgnd vps fb ton v dd max1716 MAX1854 max1855 skip d0 d1 d2 d3 d4 gnd r6 100k ? to v cc r4 100k ? r5 200k ? c2 47pf c1 0.22 f on off r2 1k ? gnd (550khz) r1 1k ? r sense 3m ? q1: (2) irf7811 international rectifier q2: (2) irf7811 international rectifier d1: cmpsh-3 central semiconductor d2: cmsh2-60 central semiconductor max1716 dac code shown figure 13. all-ceramic-capacitor application (circuit #4) 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 cs lx bst skip fb shdn v+ dh top view d0 d1 d2 d3 ton v cc ilim cc 16 15 14 13 9 10 11 12 d4 v dd pgnd dl vgate vps gnd ref qsop max1716 MAX1854 max1855 pin configuration
max1716/MAX1854/max1855 high-speed, adjustable, synchronous step-down controllers with integrated voltage positioning package information qsop.eps maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 33 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products.

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